Reducing DRAM refreshing in an error correction manner

Refreshing Thoughts on DRAM: Power Saving vs. Data Integrity

To head-off the trend of increasing power consumption and throughput overheads due to refresh in DRAM, researchers are exploring ways to fine-tune refresh rate. Refresh management proposals range from temperature-aware refresh to partitioning data cells based on volatility, with each partition having its own refresh rate. One hurdle in this area is the lack of precise description of the evaluat...

Reducing DRAM Latencies with an Integrated Memory Hierarchy Design

In this paper, we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated one-megabyte level-two cache, a processor still spends over half of its time stalling for L2 misses. Large cache blocks can improve performance, but only when coup...

Credit Expansion And Inflation In Iran: An Unrestricted Error Correction Model

A Reconfigurable Parallel Signature Analyzer for Concurrent Error Correction in DRAM

An efficient strategy to utilize a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAM’S is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log, w + 2 in the conventional Hamming code. Such an error-correction circuit (ECC) significantly improves the reliability of the memory system.

Quantum Error-Correction Codes on Abelian Groups

We prove a general form of bit flip formula for the quantum Fourier transform on finite abelian groups and use it to encode some general CSS codes on these groups.